How the Hive’s agents know a design will work before it is built

Two full-wave solvers that use different methods, run on the same board

sim_solve board takes a region of a real board, with every copper layer of its stackup, and solves it in openEMS for S-parameters. It has three known-answer cases:

• a 30 mm through line, whose |S21| is within 0.05 dB of the line formula;
• a 13 mm open stub, whose notch lands at 3.110 GHz against 3.112 GHz on paper;
• a deliberately wrong board with the line drawn twice as wide, which reads 31.2 Ω and must fail the check. It fails.

--cross-check palace then solves the same geometry with finite elements. The test case is a 2.4 GHz open-stub notch filter from the RF kit. Both solves are lossless, with zero-thickness copper and no solder mask.

Notch

2.4891 GHz (openEMS) against 2.4874 GHz (Palace), 0.07% apart. As Palace’s mesh was refined, its notch moved 2.4721 → 2.4860 → 2.4869 → 2.4874 GHz.

Whole curve

rms |ΔS| 0.017 on S11 and 0.011 on S21; the check fails above 0.05

Open

The feed impedance differs, 51.89 Ω against 50.82 Ω, and it is not known which solver is right. In Palace the 13 mm stub is 1.90% off against a 2% limit, and refining the mesh does not bring it closer. The rule for judging S11 was changed after the first result was seen, so that part is a replay, not a prediction.

Each RF line is solved twice, once in 2D and once in 3D

The board tool sizes a 50 Ω trace with a fast 2D field solve. sim_solve line then solves the same trace in openEMS in 3D. The command fails if the two disagree by more than 3%. On a 0.34 mm line on a JLC stackup they read 53.34 Ω and 53.70 Ω, 0.68% apart. The 2D tool sizes the trace with solder mask and plated copper; both of these solves leave those out, so a line built as 50 Ω reads about 53 Ω in both of them.

The chart shows the mesh check on the textbook microstrip. As the mesh is refined, the impedance goes 53.20, 52.82, 52.78, 52.75 Ω and stops at 0.2% from the formula’s 52.86 Ω.

On a 4-layer through-line board from the lab’s VNA test set, openEMS read ε_eff 2.83–2.87 against the 2D solver’s 2.851, and Z0 53.6–54.7 Ω against 53.05 Ω. That board has not been measured on a VNA yet.

Boards are simulated across part tolerances

A board goes through electrical rules, placement, design rules on the routed copper, simulation, and a manufacturing check on the real Gerber files. Every simulation bench must come with a file of pass/fail bounds, and a bench without one fails. A bench can be run at the board’s build corners, using worst-case analysis or Monte Carlo over the parts’ tolerances with a fixed seed.

Example: a 150 W, 25 MHz RF dummy load. The circuit was simulated in 48 builds: 4 resistor values × 4 launch parasitics × 3 inductances. A trimmer capacitor was tuned once, at 25 MHz. The worst return loss across 22.5–27.5 MHz is 31.3 dB, against a 20 dB spec. The launch inductance is an estimate, not a solve. The board report shows that a 3× change in it moves return loss by less than 1 dB.

Code

github.com/ihsan-sa/hwde-boards

Each gate has a fault it must catch

Every gate in the chip flow names a fault that it must catch. A set of reference designs comes with a script that plants each fault. The designs range from an 8-bit counter to a small RISC-V core, a bandgap and an SAR ADC. The suite passes only when every planted fault is caught with the expected finding and the clean reference still passes every gate. Fast gates run on every change; slow layout gates run when a change touches them. When a miss turns up on a real block, it is added to the set.

On the PLL chip

The analog benches were shown 295 faults planted in the netlist and caught 255. Each of the other 40 was ruled on individually. A ruling is accepted only if the gate’s own run confirms two things: the named measurement is the one that fault moves most, and it moves by less than max(3σ, 2%).

Defects that real designers found only after building

The agents collected public open-hardware boards where a later revision fixed a defect. Examples: a track too thin for its current, a header mirrored against the board it plugs into, MOSFET pins swapped by a footprint, an LED strip that turns on before the firmware runs. The checker is run on the broken revision and must find the defect. It is then run on the fixed revision and must report nothing.

Result: 9 of the 12 defects are found on the first revision. One more is found once the designer’s current limits are supplied. One part-rotation error in the assembly file is missed. One firmware radio fault cannot be seen in the design files at all. None of the 12 is an RF or signal-integrity defect. The checks were written with these defects in view, so this is a regression set, not an unseen test.

A block laid out again, compared file by file

An R2R DAC block was taken through every gate again on a different machine:

• The netlist, LEF and DEF were byte-identical to the first machine’s. The GDS, SDF and SPEF differed only in their export timestamps.
• Every analog gate passed again.
• A run from a clean clone, with no logs and no earlier runs, passed every gate in 19 minutes except timing. Timing failed as it had before, under an existing waiver: −0.87 ns setup slack at ss, 125 °C, 3.0 V and 50 MHz (it meets about 47 MHz). That waiver was accepted after 4 attempts to fix the violation.

The re-run found three faults in the flow and none in the design. A mutation step timed out on a busy disk. Two input hashes changed with the folder path or a file timestamp, which marked finished layouts as stale. All three are fixed.

Fabrication files regenerated and compared before an order

Every fabrication export records a SHA-256 hash for each file. Before the receiver’s boards were ordered, an agent regenerated every board’s Gerbers, parts list and placement file from the main branch in a scratch tree and compared them with the committed files. The Gerbers matched except for comment lines in the drill files. The parts lists matched. One placement file differed: a connector had been moved on purpose, and the change was traced to its pull request.

The gates alone were not enough. All gates had passed when six review agents, each given one area (power, thermal, audio, digital, parts, manufacturing), went over the boards. They returned 63 findings, including blockers. Examples: a 5 A supply path routed in 0.255 mm tracks, and a top-side-pad amplifier with no heatsink. Each blocker was fixed and recorded with its margin before the order.

A phase-locked loop on a Tiny Tapeout tile

A charge-pump PLL on GF180MCU. The oscillator, charge pump and filter are transistor-level analog laid out by code, with digital logic around them. It was submitted to Tiny Tapeout’s GF180 shuttle on 5 November 2026. On their last recorded run, 30 of its 31 gates pass:

Outside the gates

• Monte Carlo with device mismatch on (200 samples per corner): the charge-pump up/down current mismatch goes over its 10% limit in 52 of 200 samples at ff_pss and in 12 of 200 at ff_m40c_vp10. It stays inside the limit at tt and ss_pff. sim_pvt passes only because it runs with mismatch off.
• Jitter (extracted layout, simulated at 9 of the 31 corners): free-running VCO period jitter is 9.7 ps rms at tt and 13.5 ps at ff, 125 °C, VDD −10%. Locked output is about 35–60 ps rms. That figure comes from a linear model that leaves out reference, phase-detector, charge-pump and supply noise.

Code

github.com/ihsan-sa/ece298a-pll

Hive Pulse: chip, board and firmware from one spec, checked against each other

A small digital chip, the board it plugs into, and its firmware. Separate agents built each one from the same spec. The firmware’s self-tests run in simulation against the chip’s own RTL, so if two agents read the spec differently, a test fails. All 28 self-tests pass. The chip passes all 16 of its gates and Tiny Tapeout’s precheck.